IEC 62530:2007

Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language

Specifies extensions for a higher level of abstraction for modeling and verification with the Verilog hardware description language (HDL). This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI)>

OEN:

IEC

Langue:

English

Code(s) de l'ICS:

25.040.01

Statut:

Révisé

Date de Publication:

2007-11-06

Numéro Standard:

IEC 62530:2007